Senior Physical Design Engineer

Company: Annapurna Labs
Location: Cupertino
Posted on: May 3, 2021

Job Description:

Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. AWS has the broadest and deepest set of machine learning and AI services for our customers businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our success depends on our world-class infrastructure; were handling massive scale and rapid integration of emergent technologies.As a member of the Cloud-Scale Machine Learning Acceleration team youll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost.Youll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and youll work with thought-leaders in multiple technology areas. Youll have relentlessly high standards for yourself and everyone you work with, and youll be constantly looking for ways to improve our products' performance, quality and cost. Were changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.KeyResponsibilities:Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closureDrive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-offDevelop physical design methodologiesEvaluate 3rd party IP and provide recommendationsBe a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teamsBasic qualificationsBS + 10yrs or MS + 8yrs in EE/CS6+ years of experience in ASIC Physical Design from RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nmExpertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECOScripting experience with Tcl, Perl or PythonPreferred qualificationExpertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECOExperience with Full Chip Floorplan, and Integration4+ years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain.Thorough knowledge of device physics, custom/semi-custom implementation techniquesExperience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.Experience in extraction of design parameters, QOR metrics, and analyzing trendsAbility to provide mentorship, guidance to junior engineers and be a very effective team playerMeets/exceeds Amazons leadership principles requirements for this roleMeets/exceeds Amazons functional/technical depth and complexity for this roleAmazon is an Equal Opportunity Employer Minority / Women / Disability / Veteran / Gender Identity / Sexual Orientation / AgeSDL2017

Keywords: Annapurna Labs, Cupertino , Senior Physical Design Engineer, Other , Cupertino, California