Power Grid Integrity Engineer
Santa Clara Valley (Cupertino),California,United States
We are looking for applicants with experience in ASIC design
methodology with an emphasis on power grid
Strong understanding of power grid integrity and
Strong understanding of noise impact on circuit functionality
Strong communication skills and ability to work on a team since
the position requires collaborating with many
Experience in spice simulations and library
Experience in scripting.
Good technical writing skills.
Imagine yourself at the center of our SOC design effort,
collaborating with all disciplines, playing a strategic role of
getting functional products to millions of customers quickly. You
will have the opportunity to integrate and come-up with new ideas,
as well as work with a team of hardworking engineers. The main
responsibility of this role is to provide initial assessment of
power grids for new chips and new technology, define settings for
power grid simulations, and verify power grid integrity. You will
be expected to: Develop experimental flows for power integrity
analysis tools using CAD flow - simulations include input from
timing, package, and board level abstraction. Drive initial
assessment of static IR drop in power grids. Drive initial
assessment of IVD in power grids. Drive initial assessment of power
grid noise for jitter analysis. Determine settings for SoC analysis
for different type grids. Determine settings for SoC for
electro-migration/IR/IVD analysis. Work with physical design and
timing teams to analyze simulation results, verify that power grid
integrity targets are met and enhance simulation flow. Explore new
tools and methodologies for power grid integrity.
Education & Experience
BS, MS, or Ph.D. in Computer Engineering, Electrical
Engineering, or Computer Science.
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