PLL Design Engineer
Company: Apple Inc.
Posted on: June 12, 2021
At Apple, we work every single day to craft products that enrich
people's lives. Do you love working on challenges that no one has
solved yet? Do you like changing the game? We have an opportunity
for a forward-thinking and especially talented PLL Designer. As a
member of our multifaceted group, you will have the rare and
rewarding opportunity to craft upcoming products that will delight
and inspire millions of Apple's customers every day!
Apple Silicon Engineering is seeking qualified PLL designers to
work on the next generation PLLs for Apple's world-leading
systems-on-chip (SOCs). You will be part of a growing
analog/mixed-signal team involved in design and productization on
leading-edge CMOS process technology nodes.
- Understand system level requirements to create overall PLL
- Create behavioral models of PLL to drive architectural
decisions and derive block-level requirements for analog and
- Work closely with mask design team to implement layout view of
- Complete top-level spice and mixed-mode simulations to validate
- Run pre-tapeout verification flows to confirm design meets
performance, power, reliability and timing requirements.
- Define production/bench-level test plans for post-silicon
- Work with lab engineers in taking lab measurements to validate
- Review ATE and lab test results to resolve yield issues and
drive bug fixes.
- Work with system teams in system bringup and debug.
- Hold design reviews of blocks with peers/management to show
design meets spec targets and requirements.
The ideal candidate should have proven taking chips to
production with experience in the following areas:
Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum
PLLs, Digital PLL techniques, etc. High speed digital circuit
design and analysis (e.g., STA, formal verification). Digitally
assisted analog circuit and techniques. Good knowledge of band
gaps, bias, op-amps, LDOs, feedback and compensation techniques.
Experience in VCO design including but not limited to LC VCOs. Lab
and ATE test plans and measurement for characterization, and volume
Education & Experience
MSEE 3+ yrs in related area of expertise or PhD
Keywords: Apple Inc., Cupertino , PLL Design Engineer, Other , Cupertino, California
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